mirror of
https://github.com/Luzifer/cloudkeys-go.git
synced 2024-09-20 08:02:57 +00:00
Knut Ahlers
a1df72edc5
commitf0db1ff1f8Author: Knut Ahlers <knut@ahlers.me> Date: Sun Dec 24 12:19:56 2017 +0100 Mark option as deprecated Signed-off-by: Knut Ahlers <knut@ahlers.me> commit9891df2a16Author: Knut Ahlers <knut@ahlers.me> Date: Sun Dec 24 12:11:56 2017 +0100 Fix: Typo Signed-off-by: Knut Ahlers <knut@ahlers.me> commit836006de64Author: Knut Ahlers <knut@ahlers.me> Date: Sun Dec 24 12:04:20 2017 +0100 Add new dependencies Signed-off-by: Knut Ahlers <knut@ahlers.me> commitd64fee60c8Author: Knut Ahlers <knut@ahlers.me> Date: Sun Dec 24 11:55:52 2017 +0100 Replace insecure password hashing Prior this commit passwords were hashed with a static salt and using the SHA1 hashing function. This could lead to passwords being attackable in case someone gets access to the raw data stored inside the database. This commit introduces password hashing using bcrypt hashing function which addresses this issue. Old passwords are not automatically re-hashed as they are unknown. Replacing the old password scheme is not that easy and needs #10 to be solved. Therefore the old hashing scheme is kept for compatibility reason. Signed-off-by: Knut Ahlers <knut@ahlers.me> Signed-off-by: Knut Ahlers <knut@ahlers.me> closes #14 closes #15
461 lines
12 KiB
ArmAsm
461 lines
12 KiB
ArmAsm
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build 386,!gccgo,!appengine
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#include "textflag.h"
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DATA iv0<>+0x00(SB)/4, $0x6a09e667
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DATA iv0<>+0x04(SB)/4, $0xbb67ae85
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DATA iv0<>+0x08(SB)/4, $0x3c6ef372
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DATA iv0<>+0x0c(SB)/4, $0xa54ff53a
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GLOBL iv0<>(SB), (NOPTR+RODATA), $16
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DATA iv1<>+0x00(SB)/4, $0x510e527f
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DATA iv1<>+0x04(SB)/4, $0x9b05688c
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DATA iv1<>+0x08(SB)/4, $0x1f83d9ab
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DATA iv1<>+0x0c(SB)/4, $0x5be0cd19
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GLOBL iv1<>(SB), (NOPTR+RODATA), $16
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DATA rol16<>+0x00(SB)/8, $0x0504070601000302
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DATA rol16<>+0x08(SB)/8, $0x0D0C0F0E09080B0A
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GLOBL rol16<>(SB), (NOPTR+RODATA), $16
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DATA rol8<>+0x00(SB)/8, $0x0407060500030201
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DATA rol8<>+0x08(SB)/8, $0x0C0F0E0D080B0A09
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GLOBL rol8<>(SB), (NOPTR+RODATA), $16
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DATA counter<>+0x00(SB)/8, $0x40
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DATA counter<>+0x08(SB)/8, $0x0
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GLOBL counter<>(SB), (NOPTR+RODATA), $16
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#define ROTL_SSE2(n, t, v) \
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MOVO v, t; \
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PSLLL $n, t; \
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PSRLL $(32-n), v; \
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PXOR t, v
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#define ROTL_SSSE3(c, v) \
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PSHUFB c, v
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#define ROUND_SSE2(v0, v1, v2, v3, m0, m1, m2, m3, t) \
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PADDL m0, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSE2(16, t, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(20, t, v1); \
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PADDL m1, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSE2(24, t, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(25, t, v1); \
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PSHUFL $0x39, v1, v1; \
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PSHUFL $0x4E, v2, v2; \
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PSHUFL $0x93, v3, v3; \
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PADDL m2, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSE2(16, t, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(20, t, v1); \
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PADDL m3, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSE2(24, t, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(25, t, v1); \
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PSHUFL $0x39, v3, v3; \
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PSHUFL $0x4E, v2, v2; \
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PSHUFL $0x93, v1, v1
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#define ROUND_SSSE3(v0, v1, v2, v3, m0, m1, m2, m3, t, c16, c8) \
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PADDL m0, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSSE3(c16, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(20, t, v1); \
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PADDL m1, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSSE3(c8, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(25, t, v1); \
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PSHUFL $0x39, v1, v1; \
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PSHUFL $0x4E, v2, v2; \
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PSHUFL $0x93, v3, v3; \
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PADDL m2, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSSE3(c16, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(20, t, v1); \
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PADDL m3, v0; \
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PADDL v1, v0; \
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PXOR v0, v3; \
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ROTL_SSSE3(c8, v3); \
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PADDL v3, v2; \
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PXOR v2, v1; \
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ROTL_SSE2(25, t, v1); \
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PSHUFL $0x39, v3, v3; \
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PSHUFL $0x4E, v2, v2; \
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PSHUFL $0x93, v1, v1
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#define PRECOMPUTE(dst, off, src, t) \
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MOVL 0*4(src), t; \
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MOVL t, 0*4+off+0(dst); \
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MOVL t, 9*4+off+64(dst); \
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MOVL t, 5*4+off+128(dst); \
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MOVL t, 14*4+off+192(dst); \
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MOVL t, 4*4+off+256(dst); \
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MOVL t, 2*4+off+320(dst); \
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MOVL t, 8*4+off+384(dst); \
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MOVL t, 12*4+off+448(dst); \
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MOVL t, 3*4+off+512(dst); \
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MOVL t, 15*4+off+576(dst); \
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MOVL 1*4(src), t; \
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MOVL t, 4*4+off+0(dst); \
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MOVL t, 8*4+off+64(dst); \
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MOVL t, 14*4+off+128(dst); \
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MOVL t, 5*4+off+192(dst); \
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MOVL t, 12*4+off+256(dst); \
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MOVL t, 11*4+off+320(dst); \
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MOVL t, 1*4+off+384(dst); \
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MOVL t, 6*4+off+448(dst); \
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MOVL t, 10*4+off+512(dst); \
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MOVL t, 3*4+off+576(dst); \
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MOVL 2*4(src), t; \
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MOVL t, 1*4+off+0(dst); \
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MOVL t, 13*4+off+64(dst); \
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MOVL t, 6*4+off+128(dst); \
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MOVL t, 8*4+off+192(dst); \
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MOVL t, 2*4+off+256(dst); \
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MOVL t, 0*4+off+320(dst); \
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MOVL t, 14*4+off+384(dst); \
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MOVL t, 11*4+off+448(dst); \
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MOVL t, 12*4+off+512(dst); \
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MOVL t, 4*4+off+576(dst); \
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MOVL 3*4(src), t; \
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MOVL t, 5*4+off+0(dst); \
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MOVL t, 15*4+off+64(dst); \
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MOVL t, 9*4+off+128(dst); \
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MOVL t, 1*4+off+192(dst); \
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MOVL t, 11*4+off+256(dst); \
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MOVL t, 7*4+off+320(dst); \
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MOVL t, 13*4+off+384(dst); \
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MOVL t, 3*4+off+448(dst); \
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MOVL t, 6*4+off+512(dst); \
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MOVL t, 10*4+off+576(dst); \
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MOVL 4*4(src), t; \
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MOVL t, 2*4+off+0(dst); \
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MOVL t, 1*4+off+64(dst); \
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MOVL t, 15*4+off+128(dst); \
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MOVL t, 10*4+off+192(dst); \
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MOVL t, 6*4+off+256(dst); \
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MOVL t, 8*4+off+320(dst); \
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MOVL t, 3*4+off+384(dst); \
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MOVL t, 13*4+off+448(dst); \
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MOVL t, 14*4+off+512(dst); \
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MOVL t, 5*4+off+576(dst); \
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MOVL 5*4(src), t; \
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MOVL t, 6*4+off+0(dst); \
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MOVL t, 11*4+off+64(dst); \
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MOVL t, 2*4+off+128(dst); \
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MOVL t, 9*4+off+192(dst); \
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MOVL t, 1*4+off+256(dst); \
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MOVL t, 13*4+off+320(dst); \
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MOVL t, 4*4+off+384(dst); \
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MOVL t, 8*4+off+448(dst); \
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MOVL t, 15*4+off+512(dst); \
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MOVL t, 7*4+off+576(dst); \
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MOVL 6*4(src), t; \
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MOVL t, 3*4+off+0(dst); \
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MOVL t, 7*4+off+64(dst); \
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MOVL t, 13*4+off+128(dst); \
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MOVL t, 12*4+off+192(dst); \
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MOVL t, 10*4+off+256(dst); \
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MOVL t, 1*4+off+320(dst); \
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MOVL t, 9*4+off+384(dst); \
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MOVL t, 14*4+off+448(dst); \
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MOVL t, 0*4+off+512(dst); \
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MOVL t, 6*4+off+576(dst); \
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MOVL 7*4(src), t; \
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MOVL t, 7*4+off+0(dst); \
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MOVL t, 14*4+off+64(dst); \
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MOVL t, 10*4+off+128(dst); \
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MOVL t, 0*4+off+192(dst); \
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MOVL t, 5*4+off+256(dst); \
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MOVL t, 9*4+off+320(dst); \
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MOVL t, 12*4+off+384(dst); \
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MOVL t, 1*4+off+448(dst); \
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MOVL t, 13*4+off+512(dst); \
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MOVL t, 2*4+off+576(dst); \
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MOVL 8*4(src), t; \
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MOVL t, 8*4+off+0(dst); \
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MOVL t, 5*4+off+64(dst); \
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MOVL t, 4*4+off+128(dst); \
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MOVL t, 15*4+off+192(dst); \
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MOVL t, 14*4+off+256(dst); \
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MOVL t, 3*4+off+320(dst); \
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MOVL t, 11*4+off+384(dst); \
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MOVL t, 10*4+off+448(dst); \
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MOVL t, 7*4+off+512(dst); \
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MOVL t, 1*4+off+576(dst); \
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MOVL 9*4(src), t; \
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MOVL t, 12*4+off+0(dst); \
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MOVL t, 2*4+off+64(dst); \
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MOVL t, 11*4+off+128(dst); \
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MOVL t, 4*4+off+192(dst); \
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MOVL t, 0*4+off+256(dst); \
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MOVL t, 15*4+off+320(dst); \
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MOVL t, 10*4+off+384(dst); \
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MOVL t, 7*4+off+448(dst); \
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MOVL t, 5*4+off+512(dst); \
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MOVL t, 9*4+off+576(dst); \
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MOVL 10*4(src), t; \
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MOVL t, 9*4+off+0(dst); \
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MOVL t, 4*4+off+64(dst); \
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MOVL t, 8*4+off+128(dst); \
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MOVL t, 13*4+off+192(dst); \
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MOVL t, 3*4+off+256(dst); \
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MOVL t, 5*4+off+320(dst); \
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MOVL t, 7*4+off+384(dst); \
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MOVL t, 15*4+off+448(dst); \
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MOVL t, 11*4+off+512(dst); \
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MOVL t, 0*4+off+576(dst); \
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MOVL 11*4(src), t; \
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MOVL t, 13*4+off+0(dst); \
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MOVL t, 10*4+off+64(dst); \
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MOVL t, 0*4+off+128(dst); \
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MOVL t, 3*4+off+192(dst); \
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MOVL t, 9*4+off+256(dst); \
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MOVL t, 6*4+off+320(dst); \
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MOVL t, 15*4+off+384(dst); \
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MOVL t, 4*4+off+448(dst); \
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MOVL t, 2*4+off+512(dst); \
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MOVL t, 12*4+off+576(dst); \
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MOVL 12*4(src), t; \
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MOVL t, 10*4+off+0(dst); \
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MOVL t, 12*4+off+64(dst); \
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MOVL t, 1*4+off+128(dst); \
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MOVL t, 6*4+off+192(dst); \
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MOVL t, 13*4+off+256(dst); \
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MOVL t, 4*4+off+320(dst); \
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MOVL t, 0*4+off+384(dst); \
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MOVL t, 2*4+off+448(dst); \
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MOVL t, 8*4+off+512(dst); \
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MOVL t, 14*4+off+576(dst); \
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MOVL 13*4(src), t; \
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MOVL t, 14*4+off+0(dst); \
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MOVL t, 3*4+off+64(dst); \
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MOVL t, 7*4+off+128(dst); \
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MOVL t, 2*4+off+192(dst); \
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MOVL t, 15*4+off+256(dst); \
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MOVL t, 12*4+off+320(dst); \
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MOVL t, 6*4+off+384(dst); \
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MOVL t, 0*4+off+448(dst); \
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MOVL t, 9*4+off+512(dst); \
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MOVL t, 11*4+off+576(dst); \
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MOVL 14*4(src), t; \
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MOVL t, 11*4+off+0(dst); \
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MOVL t, 0*4+off+64(dst); \
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MOVL t, 12*4+off+128(dst); \
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MOVL t, 7*4+off+192(dst); \
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MOVL t, 8*4+off+256(dst); \
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MOVL t, 14*4+off+320(dst); \
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MOVL t, 2*4+off+384(dst); \
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MOVL t, 5*4+off+448(dst); \
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MOVL t, 1*4+off+512(dst); \
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MOVL t, 13*4+off+576(dst); \
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MOVL 15*4(src), t; \
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MOVL t, 15*4+off+0(dst); \
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MOVL t, 6*4+off+64(dst); \
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MOVL t, 3*4+off+128(dst); \
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MOVL t, 11*4+off+192(dst); \
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MOVL t, 7*4+off+256(dst); \
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MOVL t, 10*4+off+320(dst); \
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MOVL t, 5*4+off+384(dst); \
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MOVL t, 9*4+off+448(dst); \
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MOVL t, 4*4+off+512(dst); \
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MOVL t, 8*4+off+576(dst)
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// func hashBlocksSSE2(h *[8]uint32, c *[2]uint32, flag uint32, blocks []byte)
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TEXT ·hashBlocksSSE2(SB), 0, $672-24 // frame = 656 + 16 byte alignment
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MOVL h+0(FP), AX
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MOVL c+4(FP), BX
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MOVL flag+8(FP), CX
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MOVL blocks_base+12(FP), SI
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MOVL blocks_len+16(FP), DX
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MOVL SP, BP
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MOVL SP, DI
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ADDL $15, DI
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ANDL $~15, DI
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MOVL DI, SP
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MOVL CX, 8(SP)
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MOVL 0(BX), CX
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MOVL CX, 0(SP)
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MOVL 4(BX), CX
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MOVL CX, 4(SP)
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XORL CX, CX
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MOVL CX, 12(SP)
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MOVOU 0(AX), X0
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MOVOU 16(AX), X1
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MOVOU counter<>(SB), X2
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loop:
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MOVO X0, X4
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MOVO X1, X5
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MOVOU iv0<>(SB), X6
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MOVOU iv1<>(SB), X7
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MOVO 0(SP), X3
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PADDQ X2, X3
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PXOR X3, X7
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MOVO X3, 0(SP)
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PRECOMPUTE(SP, 16, SI, CX)
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ROUND_SSE2(X4, X5, X6, X7, 16(SP), 32(SP), 48(SP), 64(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+64(SP), 32+64(SP), 48+64(SP), 64+64(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+128(SP), 32+128(SP), 48+128(SP), 64+128(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+192(SP), 32+192(SP), 48+192(SP), 64+192(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+256(SP), 32+256(SP), 48+256(SP), 64+256(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+320(SP), 32+320(SP), 48+320(SP), 64+320(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+384(SP), 32+384(SP), 48+384(SP), 64+384(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+448(SP), 32+448(SP), 48+448(SP), 64+448(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+512(SP), 32+512(SP), 48+512(SP), 64+512(SP), X3)
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ROUND_SSE2(X4, X5, X6, X7, 16+576(SP), 32+576(SP), 48+576(SP), 64+576(SP), X3)
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PXOR X4, X0
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PXOR X5, X1
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PXOR X6, X0
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PXOR X7, X1
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LEAL 64(SI), SI
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SUBL $64, DX
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JNE loop
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MOVL 0(SP), CX
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MOVL CX, 0(BX)
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MOVL 4(SP), CX
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MOVL CX, 4(BX)
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MOVOU X0, 0(AX)
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MOVOU X1, 16(AX)
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MOVL BP, SP
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RET
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// func hashBlocksSSSE3(h *[8]uint32, c *[2]uint32, flag uint32, blocks []byte)
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TEXT ·hashBlocksSSSE3(SB), 0, $704-24 // frame = 688 + 16 byte alignment
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MOVL h+0(FP), AX
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MOVL c+4(FP), BX
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MOVL flag+8(FP), CX
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MOVL blocks_base+12(FP), SI
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MOVL blocks_len+16(FP), DX
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MOVL SP, BP
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MOVL SP, DI
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ADDL $15, DI
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ANDL $~15, DI
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MOVL DI, SP
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MOVL CX, 8(SP)
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MOVL 0(BX), CX
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MOVL CX, 0(SP)
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MOVL 4(BX), CX
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MOVL CX, 4(SP)
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XORL CX, CX
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MOVL CX, 12(SP)
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MOVOU 0(AX), X0
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MOVOU 16(AX), X1
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MOVOU counter<>(SB), X2
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loop:
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MOVO X0, 656(SP)
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MOVO X1, 672(SP)
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MOVO X0, X4
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MOVO X1, X5
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MOVOU iv0<>(SB), X6
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MOVOU iv1<>(SB), X7
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MOVO 0(SP), X3
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PADDQ X2, X3
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PXOR X3, X7
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MOVO X3, 0(SP)
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MOVOU rol16<>(SB), X0
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MOVOU rol8<>(SB), X1
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PRECOMPUTE(SP, 16, SI, CX)
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ROUND_SSSE3(X4, X5, X6, X7, 16(SP), 32(SP), 48(SP), 64(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+64(SP), 32+64(SP), 48+64(SP), 64+64(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+128(SP), 32+128(SP), 48+128(SP), 64+128(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+192(SP), 32+192(SP), 48+192(SP), 64+192(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+256(SP), 32+256(SP), 48+256(SP), 64+256(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+320(SP), 32+320(SP), 48+320(SP), 64+320(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+384(SP), 32+384(SP), 48+384(SP), 64+384(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+448(SP), 32+448(SP), 48+448(SP), 64+448(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+512(SP), 32+512(SP), 48+512(SP), 64+512(SP), X3, X0, X1)
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ROUND_SSSE3(X4, X5, X6, X7, 16+576(SP), 32+576(SP), 48+576(SP), 64+576(SP), X3, X0, X1)
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MOVO 656(SP), X0
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MOVO 672(SP), X1
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PXOR X4, X0
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PXOR X5, X1
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PXOR X6, X0
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PXOR X7, X1
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LEAL 64(SI), SI
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SUBL $64, DX
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JNE loop
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MOVL 0(SP), CX
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MOVL CX, 0(BX)
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MOVL 4(SP), CX
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MOVL CX, 4(BX)
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MOVOU X0, 0(AX)
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MOVOU X1, 16(AX)
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MOVL BP, SP
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RET
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// func supportSSSE3() bool
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TEXT ·supportSSSE3(SB), 4, $0-1
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MOVL $1, AX
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CPUID
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MOVL CX, BX
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ANDL $0x1, BX // supports SSE3
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JZ FALSE
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ANDL $0x200, CX // supports SSSE3
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JZ FALSE
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MOVB $1, ret+0(FP)
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RET
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FALSE:
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MOVB $0, ret+0(FP)
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RET
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// func supportSSE2() bool
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TEXT ·supportSSE2(SB), 4, $0-1
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MOVL $1, AX
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CPUID
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SHRL $26, DX
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ANDL $1, DX // DX != 0 if support SSE2
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MOVB DX, ret+0(FP)
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RET
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